1. Field of the Invention
This invention relates to the field of data transfer circuits. More particularly, this invention relates to a technique of calibrating an impedance of a data transfer circuit.
2. Description of the Prior Art
It is known to provide data transfer circuits, such as off-chip driver circuits and on-die termination circuits, associated with integrated circuits that have a requirement that their impedance is accurately matched to some known level. One example is in the case of double data rate memory (DDR memory) in which data transfers happen at both edges of the clock signal and the timing constraints are critical for correct data transfer. A competing factor is that as process geometries become smaller there is a great degree of variation in the performance of the circuits across PVT (process, voltage and temperature).
In order to address the above requirements it is known to provide calibration circuits in association with data transfer circuits. FIG. 1 of the accompanying drawings schematically illustrates a DDR memory integrated circuit 2 including a plurality of off-chip driver circuits 4 connected via pads 6 to circuitry external of the integrated circuit 2. In a similar manner, on-die termination circuits 8 are connected via pads 10 to other off-chip circuitry. Calibration circuitry 12, 14 associated respectively with the on-die termination circuits 8 and the off-chip driver circuits 4 are used to generate respective calibration signals supplied to the on-die termination circuits 8 and the off-chip driver circuits 4.
FIG. 2 of the accompanying drawings schematically illustrates a data transfer circuit in the form of an off-chip driver circuit 4 that is responsive to a calibration signal in the form of a 4-bit signal [P3:P0] supplied to the P-type transistors driving the pad 6 via a poly resistor 16. Another 4-bit calibration value [N3:N0] is used to control the N-type transistors driving the pad 6 via a different poly resistor. The 4-bit calibration value for the P-type transistors is used to switch main transistors 20, 22, 24, 26 between a high impedance state and a low impedance state. These transistors have different sizes (width) and may conveniently be provided to have impedances that vary by a factor of two between each other. Thus, main transistor 26 has an size of X and an impedance of 8Y when it is in its low impedance state whereas transistors 24, 22 and 20 respectively have impedances of 4Y, 2Y and Y when they are in their low impedance state. The transistor can be considered to have an effectively infinite impedance when in their high impedance state (i.e. switched off). The same arrangement applies in respect of the N-type transistors also illustrated in FIG. 2. By varying the 4-bit calibration values supplied to the circuitry of FIG. 2, the output impedance of this off-chip driver circuit 4 may be varied. The total impedance is given by the poly resistors 16, 18 with their respective main transistors subject to the calibration value control in order to fine-tune the impedance to a desired level.
FIG. 3 of the accompanying drawings schematically illustrates a portion of calibration circuitry 14. This calibration circuitry also includes main transistors 28, 30, 32 and 34 of different physical sizes and accordingly different impedances that are controlled by different bit signals within a 4-bit calibration value. A poly resistor 38 connects the main transistors 28, 30, 32, 34 to a pad 36 and on to an off-chip resistor 40 with a known value, such as Rexternal Ohms. In operation, the 4-bit calibration value is changed to different values to produce different combinations of the main transistors 28, 30, 32, 34 being in their low impedance state as opposed to their high impedance state.
FIG. 4 of the accompanying drawings illustrates, using a voltage waveform having a stair case form, the operation of the calibration circuitry of FIG. 3. In particular, different calibration values are applied in a sequence starting from “1111” and decrementing as a binary number. Each of these different calibration values will produce a different combined impedance for the main transistors 28, 30, 32, 34 which are connected in parallel. The calibration circuitry monitors the voltage at the pad 36 and when this crosses the midway point between ground and the supply voltage DVdd, then this indicates (in this example embodiment) that the combined impedance being calibrated has the desired relationship with the external predetermined resistor 40.
FIG. 5 and FIG. 6 of the accompanying drawings are voltage waveforms that illustrate the situation in which the combined impedances monotonically varied until a threshold impedance is crossed corresponding to the midway voltage between the supply and the ground being measured at the pad 36. The calibration value determined is the value which resulted in the threshold impedance being crossed. This calibration value is then supplied to at least the nearby off-chip driver circuits 4 to control their impedance.